|
|
 |
|
|
| Job details |
|
| If you want to remember this job or apply at a later time, click Save job to save it to your personal folder. |
|
| SENIOR DFT ENGINEER |
|
| Description |
SENIOR DFT ENGINEER #1241745
As a DFT engineer at NVIDIA, you'll be responsible for cutting edge DFT involving implementing key DFT logic modules, and verifying them. These include test mode controllers, IO bist, Memory Bist, Jtag. In addition you will be responsible for mbist, scan insertion and ATPG and post silicon validation.
MINIMUM REQUIREMENTS:
- BSEE required, MSEE preferred.
- 4 to 7 years of experience in DFT / design field.
- Strong logic Design and verification back ground with experience in STA.
- Must possess a strong knowledge of DFT including scan, BIST, on-chip scan compression, fault models, ATPG, and fault simulation.
- Programming in Perl, tcl and c++ is a plus
EOE |
|
|
 |
|
|
