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| Job details |
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| SR. STANDARD CELL AND DATA-PATH CELL CIRCUIT DESIGNER |
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| Description |
SR. STANDARD CELL AND DATA-PATH CELL CIRCUIT DESIGNER #1145716
RESPONSIBILITIES:
- To develop circuit/layout methodology for high performance standard cells and data path cells with dynamic circuit design preferred.
- Plan to minimize the efforts considering different design rules and electrical parameters for multiple foundries
- Transistor level circuit design with layout floor planning and supervisions.
- Circuit simulations, layout extractions, timing/power characterizations and lib file generations.
- Circuit level logical function and transistor level verifications.
- Understand power gating strategy including decoupling cap cell design.
MINIMUM REQUIREMENTS:
- BSEE minimum, MSEE or PhD Preferred.
- Candidate should have at least 5+ years of circuit design experience in a custom or semi-custom IC design environment..
- Design experience in 45nm (or below) cmos process is highly desired.
- Ideal candidates will have prior experience in success of delivering design to production.
- Must possess strengths in transistor level circuit design.
- Will need to interface with logic designers and understand verilog.
- Proficient in standard custom design environments and tools.
- Some experience in an ASIC flow environment preferred.
- Knowledge in clock buffer requirements and high performance flop designs.
EOE |
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