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| Job details |
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| SR ASIC / METHODOLOGY ENGINEER |
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| Description |
SENIOR ASIC / METHODLOGY ENGINEER #1230945
As a senior member of our ASIC team, you'll be working on streamlining the chip infrastructure process across product designs, focusing on such tasks as: netlist manipulation, clocks, timing convergence, design for test, and low power operation. Specifically you' be focusing on methodologies for full chip layout planning (partitioning, planning clock distribution, power control and other structures), full chip timing closure (primetime scripts, other tools, etc) and gate-level design of high-speed logic.
RESPONSIBILITIES:
- Develop advanced methodologies for chip level integration, floorplanning, physical partitioning, and low power design.
- Develop configurable timing flows using commercial timing tools (Primetime, Goldtime, etc) for timing analysis and closure, noise analysis, clock skew analysis, special circuits such as clock dividers, core logic <-> IO macros interfaces such as PCI-E, Frame-Buffer/Memory, TMDS, etc.
- Develop scripts for performing ECO's.
- Collaborate and deploy methodologies for advanced design architectures.
MINIMUM REQUIREMENTS:
- BS or MS in Electrical Engineering or Computer Science
- 7 - 10 years of relevant full chip ASIC design experience ideally with a focus in timing and physical design
- Good software and scripting skills.
EOE |
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